Method of generating a labeled image and image processing system with pixel blocks

ABSTRACT

To identify pixels constituting image elements for generating a labeled image in which pixels are labeled with identification information, a pixel block including four pixels adjacent to one another in two dimensions is inputted as a unit from data including pixels that form an image. All of the on-pixels that are subject for grouping, included in the pixel block are labeled with the same identifier. Since the on-pixels that are included in a pixel block are consecutively connected, such pixels can be labeled with the same identifier without having to calculate whether such pixels are connected.

TECHNICAL FIELD

The present invention relates to a method of labeling used forextracting image elements and other purposes.

BACKGROUND ART

A labeling process that assigns labels to pixels of connected componentsis known as a basic method for processing two-dimensional images.Japanese Laid-Open Patent Publication No. H07-192130 discloses aprovisional labeling process of a labeling process that is carried outusing a one-dimensional SIMD (Single Instruction stream Multiple Datastream) processor. In the disclosed technique, a process of provisionallabeling is carried out on each row in an image in order using theone-dimensional SIMD processor.

Japanese Laid-Open Patent Publication No. 2002-230540 discloses alabeling process carried out in parallel for pixels in a diagonaldirection in a pixel array in an input image by a plurality of PEs(processing elements) in a one-dimensional SIMD processor. By processinga plurality of pixels in the diagonal direction in parallel, labelingcan be carried out for the pixels that are adjacent of a target pixeland would be connecting to the target pixel before labeling the targetpixel. By doing so, effective use is made of the parallel processingability of the SIMD processor and therefore the processing speed isincreased. To realize this method however, even for an image with aresolution of around 200 dpi, a one-dimensional SIMD processor withseveral thousand PEs are required to scan in the diagonal direction.

DISCLOSURE OF THE INVENTION

One aspect of the present invention is a method of generating a labeledimage, including the steps of:

-   a1. inputting a pixel block, which includes a plurality of pixels    that are adjacent to one another in more than one dimension, as a    single unit from data including pixels for forming an image; and-   a2. labeling, based on binarized pixels, all on-pixels or all    off-pixels that subject for grouping and are included in the pixel    block with common identification information.

If the image is a two-dimensional image, the pixel block is composed of2×2=4 pixels that are adjacent to one another in two dimensions.Conversely, if the image is a three-dimensional image, the pixel blockis composed of 2×2×2=8 pixels that are adjacent to one another in threedimensions. Each pixel included in a pixel block is adjacent to all ofthe other pixels included in the pixel block. When grouping orsegmenting pixels composing an image is performed, based on a binarizedimage, by labeling pixels that are connected in eight directions withthe same or common identification information, among the pixels includedin a pixel block, all the pixels that are subjects for grouping, thatis, all the pixels with the same state or value (i.e., all on-pixelsthat are ON (“1”) or all off-pixels that are OFF (“0”)) in the pixelblock can be labeled with the common identification information.Accordingly, a process that assigns identification information toindividual pixels for grouping included in the pixel block is notrequired, and parallel processing with the plurality of pixels includedin a pixel block becomes possible. It is therefore possible to improvethe speed of the process that includes generating a labeled image inwhich the pixels have been labeled with identification information.

One of other aspects of the present invention is an image processingsystem including:

-   b1: an interface configured for inputting data including a plurality    of pixels, which are adjacent in more than one dimension and compose    a pixel block, in parallel from data including pixels for forming an    image; and-   b2. a labeling processor configured for labeling, based on binarized    pixels, all on-pixels or all off-pixels that are subject for    grouping and are included in the pixel block with common    identification in parallel.

In the image processing system, a plurality of pixels that compose apixel block are input in parallel and the plurality of pixels arelabeled with the common identification information in parallel. Theimage processing system preferably includes a processor equipped with aprocessing region that includes a plurality of processing elements and,in the processing region, a plurality of data paths that operate inparallel are configured by the plurality of the processing elements. Theinterface and the labeling processor can be configured in the processingregion of the processor and it is possible to provide the processor thatcan execute the process that inputs a plurality of pixels and theprocess that labels the plurality of pixels by pipeline processing.

Further one of other aspects of the present invention is an imageprocessing method, including the steps of:

-   c1. inputting a pixel block, which includes a plurality of pixels    that are adjacent to one another in more than one dimension, as a    single unit from data including a plurality of pixels for forming an    image;-   c2. labeling, based on binarized pixels, all on-pixels or all    off-pixels for grouping that are included in the pixel block, with    same identification information; and-   c3. distinguishing image elements in a labeled image.

Distinguishing image elements leads identifying the image elements,extracting the image elements, and calculating characteristic values ofthe image elements. The characteristic values (characteristic amounts)include a one-dimensional or two-dimensional moment, an area, a boundarylength, a density, a width, and other values of the image element. Ifthe image is a three-dimensional, the characteristic values of the imageelements include a volume (cubic content), a center of gravity, amoment, and other values. Identifying the image elements and finding thecharacteristic values thereof are effective for many applications thatinclude a process where it is necessary to recognize an image. Using alabeled image, an industrial robot that carries out automatic mountingcan judge the position and tilting of a component that has beenattached. In an automatic driving apparatus, a labeled image is used torecognize the road or obstacles. In a three-dimensional CT scan, thelabeled image is used in a process for having basic characteristics of abody of an image, or preprocessing for the same.

The process for generating a labeled image preferably include a firststage and a second stage; the first stage including scanning an image,labeling with provisional identification information showing therelationship with pixels in the vicinity, and generating connecting(linking or combining) information for the provisional identificationinformation; and the second stage including labeling with realidentification information showing image elements based on theprovisional identification information and the connecting informationthereof. The step of inputting and the step of labeling described abovecan be applied to the first stage and the second stage respectively, andthe processing speed of the respective stages can be improved.

The image processing system is provided that includes a first processingsystem and a second processing system; the first processing system beingfor scanning the image, labeling with the provisional identificationinformation, and generating connecting information for theidentification information; and the second processing system being forlabeling with real identification information showing image elementsbased on the connecting information. The first processing system and thesecond processing system respectively include the interface and thelabeling processor, wherein the labeling processor of the firstprocessing system assigns the provisional identification information asthe common identification information for labeling, and the labelingprocessor of the second processing system assigns the realidentification information as the common identification information forlabeling. The image processing system preferably includes areconfigurable processor equipped with a processing region and a controlunit for reconfiguring the processing region. The interface and thelabeling processor included in the first processing system and theinterface and the labeling processor included in the second processingsystem can be configured in the processing region after the processingof the respective processing system has ended. By configuring the firstprocessing system and the second processing system at different timingin the processing region, it is possible to make effective use of thehardware resources of the processor and to provide a small-scale imageprocessing system with high performance.

A reconfigurable integrated circuit device such as an FPGA equipped witha plurality of processing units is one of hardware that includes afunction for performing many processes in parallel. The reconfigurableintegrated circuit device disclosed by WO02/095946 filed by the presentapplicant is suited to the above image processing system since thecircuit configuration can be dynamically changed.

In the first stage and the first processing system, at the labeling withthe provisional identification information, pixel blocks are units forlabeling with the provisional identification information. Accordingly,the provisional identification information for labeling is selected notfor (unit of) individual pixel but for (unit of) pixel block units. Inthe first stage and the first processing system, at the labeling withthe provisional identification information, a pixel block is inputtedtogether with an adjacent pixel group including pixels that have alreadybeen labeled with the provisional identification information. Thefollowing steps are carried out in pixel block units for labeling withprovisional identification information:

-   d1. inheriting, when the adjacent pixel group includes inheritable    provisional identification information, the inheritable provisional    identification information as the common identification information;-   d2. recording, when the adjacent pixel group includes other    inheritable provisional identification information, connecting    information for the inherited provisional identification information    and non-inherited provisional identification information; and-   d3 setting, when the adjacent pixel group does not include    inheritable provisional identification information, new provisional    identification information as the common identification information.

The processor for labeling with the provisional identificationinformation can be configured for pipeline processing a process thatdecodes the pixel block and the adjacent pixel group; and a process thatlabels the pixels for grouping in the pixel block with selected one ofthe inheritable provisional identification information and the newprovisional identification information as the common identificationinformation. The second stage that is executed after the first stage andlabels with real identification information as the common identificationinformation includes the step of inputting and the step of labeling thatare independent of the first stage, wherein in the step of labeling,based on the connecting information, the real identification informationthat is common to pixel blocks in a connecting relationship is assignedas the common identification information for labeling.

One of the labeled images has the identification information forsegmenting image elements in which pixels are consecutive or connected.For generating such labeled image, in the first stage and the firstprocessing system, a pixel block composed of four pixels adjacent to oneanother in two dimensions and an adjacent pixel group composed of sixpixels that are adjacent to two adjacent edges of the pixel block areinputted, and when both the pixel block and the adjacent pixel groupinclude pixels that compose an image element in which the pixels areconsecutive, the provisional identification information included in theadjacent pixel group is inherited. It is also possible to input aplurality of pixel blocks and adjacent pixel group related to the pixelblocks and to label pixels included therein that compose connected imageelements with the common provisional identification information.

In the method where all of the pixels for grouping included in a pixelblock are labeled with the common identification information, it is notjudged whether the pixels for grouping included in the pixel block areconsecutively connected. When the range labeled with the commonidentification information is a pixel block that includes only 2×2pixels, the pixels connected in eight directions are identified by thecommon identification information. By increasing the number of pixelsincluded in one pixel block and/or labeling the pixel blocks having somerelationship with the common identification information, it is possibleto label pixels that are not necessarily consecutively connected, withthe common identification information. According to this type oflabeling, it is possible to roughly group pixels included inhigh-resolution pixel data. That is, pixels that are not connected canbe grouped together according to predetermined conditions. In addition,since it is possible to collectively assign the same identificationinformation to pixels included in a pixel block using parallelprocessing, the processing speed of the labeling process is improved.Since no process that changes the image resolution is included in thelabeling procedure according to the present method, it is possible toassign identification information that has been roughly grouped tohigh-resolution image data without deterioration in the precision of theimage data.

In the first stage and the first processing system, when at least onepixel block and an adjacent pixel group including at least one pixelblock that is adjacent to the at least one pixel block are inputted, andwhen both the at least one pixel block and the adjacent pixel groupinclude pixels for grouping, provisional identification informationincluded in the adjacent pixel group is inherited. So long as pixels arepresent in a range in which pixel blocks are interrelated, provisionalidentification information is inherited even if the pixels are notconsecutive or connected. Accordingly, it is possible to assign thecommon identification information to pixels that have some range ofrelationship exceeding a range where the pixels are connected.

In the first stage and the first processing system, when a large pixelblock composed of four pixel blocks that are adjacent to one another intwo dimensions and an adjacent pixel group composed of six pixel groupsthat are adjacent to two adjacent edges of the large pixel block areinputted, and when both the large pixel block and the adjacent pixelgroup include pixels for grouping, provisional identificationinformation included in the adjacent pixel group can be inherited. Thelarge pixel block including four pixel blocks is composed of sixteenpixels. Accordingly, it is possible to assign the common identificationinformation to pixels in a range in which four pixel blocks and sixpixel blocks that are adjacent to the four pixel blocks are related,thereby grouping such pixels together. With this type of labeling,sixteen pixels can be labeled in parallel, and to do so, forty pixelsincluded in a large pixel block and the adjacent pixel group, areprocessed in parallel. This method is suited to implementation inhardware (a processor) with a large number of processing elements thatoperate in parallel. Although the logic relating to inheritance willbecome complex, it is also possible to input a plurality of large pixelblocks and adjacent pixel group related thereto and to label the pixelsin parallel.

In the second stage and the second processing system for labeling withreal identification information, it is also possible to set, based onthe connecting information, real identification information that iscommon to large pixel blocks in a connecting relationship as the commonidentification information and to label all of the pixels for groupingincluded in the large pixel block with the real identificationinformation. In this stage of relabeling where some of the provisionalidentification information is combined, sixteen or more pixels can belabeled with the real identification information in parallel.

Further on of other aspects of the present invention is a method ofanalyzing an image, including the steps of:

-   e1. inputting a pixel block, which includes a limited number of    pixels that are adjacent to one another in more than one dimension,    as a single unit from data including pixels for forming an image;-   e2 labeling, based on binarized pixels, all on-pixels or all    off-pixels that are subject for grouping, included in the pixel    block with common identification information; and-   e3 calculating characteristic values of respective image elements by    repeatedly carrying out an operation in units that include at least    one pixel block.

In the step of labeling, the same or common identification informationis collectively assigned to the pixels included in one pixel block as aunit. Since the image elements are assembled with pixel blocks, byrepeating an operation in units that include pixel blocks, it ispossible to calculate characteristic values of the respective imageelements. The image processing system also preferably includes a firstprocessor configured to calculate characteristic values of therespective image elements by repeating an operation in units thatinclude at least one pixel block. When the image processing systemincludes a reconfigurable processor, the first processor can bereconfigured in the processing region at appropriate timing after theprocessing of the first processing system has been completed.

It is preferable for the method to further include a process that isexecuted in parallel with the labeling and calculates, in units of thepixel blocks under the labeling, block characteristic values thatcontribute to characteristic values of image elements. Finding thecharacteristic values of the respective pixel blocks is effective aspreprocessing when finding the total of the characteristic values of theimage elements grouped together using the identification information. Inthe process that calculates the block characteristic values, it ispossible to find characteristic amounts using binarized pixels and it isalso possible to calculate the block characteristic values frommultivalue pixels included in the labeled pixel blocks. Accordingly, aprocess that finds a characteristic value from multivalue pixelsincluding gray level information can be carried out in parallel to thelabeling process and in particular the process for labeling withprovisional identification information, and therefore it becomespossible to omit the processing time required to reaccess the image dataincluding gray level information based on the labeled information.

The image processing system preferably further includes a secondprocessor that is supplied by the interface with data including a pixelblock in parallel with the labeling processor and is configured tocalculate block characteristic values that contribute to characteristicvalues of image elements in units of the pixel blocks under thelabeling. The second processor should preferably be configured tocalculate values that contribute to the characteristic values of imageelements from multivalue pixels included in pixel blocks under thelabeling.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows scanning an image in units of pixel blocks.

FIG. 2( a) shows an enlargement of the arrangements of a pixel block andan adjacent pixel group and FIG. 2( b) shows the arrangement ofprovisional identifiers (provisional IDs).

FIG. 3( a) to FIG. 3( d) respectively shows the combinations of thepixel arrangements of the pixel block and the adjacent pixel group forselecting a provisional identifier.

FIG. 4 is a table in which combinations of the pixel arrangement of thepixel block and the adjacent pixel group for selecting the provisionalidentifier are collectively shown.

FIG. 5 shows scanning an image in units of large pixel blocks.

FIG. 6( a) shows an enlargement of the arrangement of a large pixelblock and an adjacent pixel group and FIG. 6( b) shows the arrangementof provisional identifiers (provisional IDs).

FIG. 7( a) to FIG. 7( d) respectively shows the combinations of thepixel arrangements of the large pixel block and the adjacent pixel groupfor selecting the provisional identifier.

FIG. 8 is a flowchart showing an overview of image processing.

FIG. 9 schematically shows the construction of a reconfigurableprocessing device suited to image processing.

FIGS. 10( a) to 10(c) show the configuration of an image processingapparatus that uses the reconfigurable processing device.

FIG. 11 schematically shows the configuration of an interface and alabeling processor of a first stage for labeling with provisionalidentifiers.

FIG. 12 schematically shows the configuration of a logic part of thelabeling processor shown in FIG. 11.

FIG. 13 schematically shows the configuration of a processor (a secondprocessor) that analyzes gray levels.

FIG. 14 schematically shows the configuration of a threshold unit of theprocessor shown in FIG. 13.

FIG. 15 schematically shows gray level data.

FIG. 16 schematically shows the configuration of an interface and alabeling processor of a second stage for labeling with real identifiers.

FIG. 17 schematically shows the configuration of an analysis processor(a first processor) that carries out a process for extracting a maximumvalue in the Y direction.

BEST MODE FOR CARRYING OUT THE INVENTION

1. Basic Concept of Block Labeling

FIG. 1 shows the basic concept of block labeling. Here, a binarizedtwo-dimensional image (a binary image) 1 to be outputted (displayed,printed, etc.) in frame units is used as an example image. The image 1is a two-dimensional array of a plurality of pixels 5 that each have avalue of “0” (OFF) or “1” (ON). By generating a labeled image where thepixels 5 have been labeled with identification information, it ispossible to analyze the information included in the image data includingthe pixels 5. Image elements composed of pixels 5 that are in apredetermined relationship are segmented or distinguished from theinformation in the image 1 so that the image 1 can be automaticallyanalyzed or specific elements in the image 1 can be shown to the userand analyzed further.

Conventional labeling is used to segment or classify elements (areas orparts, referred to as “image elements” in the present specification)where pixels 5 are consecutively connected. Block labeling herein can beused to segment image elements where the pixels 5 are consecutive andcan also be used to segment image elements from pixels 5 that are notconsecutive but have a predetermined relationship. In the presentspecification, identifying pixels 5 that are not consecutive but have apredetermined relationship and also identifying consecutive pixels 5 arecalled “grouping”. In particular, the identifying pixels 5 that are notconsecutive but have a predetermined relationship is sometimes referredto as “rough grouping”. A block labeling process makes grouping, thatincludes the rough grouping possible and therefore even when the pixels5 are not consecutive, it becomes possible to judge that pixels that arein a given range or have a given distance relationship compose a singleelement in the image. On of the rough grouping identifies pixels thatare several pixels away at most, including consecutive pixels, asbelonging to the same group.

In a binary image, it is possible to treat compositions (elements) madeup of on-pixels, which are pixels that are ON (i.e., that have the value“1”), as image elements, contrary it is also possible to treatcompositions (elements) made up of off-pixels, which are pixels that areOFF (i.e., that have the value “0”), as image elements. In An exampleimage described below includes image elements composed of on-pixels(value “1”). Accordingly, in an example method of block labelingdescribed, the on-pixels having value “1” are labeled withidentification information as pixels that are subjects for grouping. Itis also possible to carry out the block labeling process for groupingoff-pixels having value “0” using the similar method.

1.1 Identifying Image Elements where Pixels are Connected

FIG. 1 and FIG. 2 show an example method of block labeling pixels thatrelate to image elements where pixels are connected. In a process thatgenerates a labeled image where pixels have been labeled withidentification information used to distinguish image elements, it isnecessary to judge how the large number of pixels included in a singleimage are connected. In a two-dimensional image, an “image element” is aconnected region that extends in two dimensions. A large amount ofmemory is required to search for image elements in two dimensions, andsince there is a high probability of duplicated processing, theprocessing is normally inefficient. In this method, first, a search iscarried out in direction of one dimension to judge whether respectivepixels are connected to other pixels that have already been labeled withprovisional identification information and label the respective pixelswith provisional identification information. During the labeling withprovisional identification information while scanning an image, when anidentifier of the provisional identification information that hasassigned is connected to the other identifier of the provisionalidentification information that has also assigned at the later stage,one of the identifiers is inherited and connecting information for theconnected identifiers of the provisional identification information isgenerated. When the scanning of the image is complete and the connectinginformation is aggregated for the image, “real” identificationinformation showing connected elements are selected using theprovisional identification information and the connecting informationfor the provisional identification information, then a labeled imagewhere the pixels are relabeled with real identification information isgenerated. From this labeled image, it is possible to distinguishindependent image elements which can be used in a variety of imageprocessing.

In the block labeling process, when labeling the pixels 5 that arearranged in two dimensions, instead of processing the pixels 5 one byone or processing in one dimension such as in row units, four pixels 5that are adjacent above, below, left, and right are processed inparallel as a single unit (called a “pixel block”). A pixel block 2 is a2×2 and a two-dimensional array, and the pixels 5 included in the pixelblock 2 are adjacent to one another. Accordingly, if it is assumed thatthere are eight directions in which pixels can be connected, if a pixelblock 2 includes pixels that are “1”, all of the on-pixels 5 included inthe pixel block 2 are connected with no need for further logicoperations, and the common identification information, for example, thesame identification data (an identifier) such as a label, willdefinitely be assigned to each pixel. This means that by carrying outlabeling pixels in pixel blocks 2 as units, a 2×2 array of four pixels 5is processed in parallel and simultaneously it is possible to omitprocessing for logic operations regarding the relationship between thefour pixels 5.

The direction of scanning that has pixel blocks 2 as units can be any ofup, down, left and right. In the present embodiment, block labeling iscarried out with the left to right direction (Y direction) for the image1 shown in FIG. 1 as the scanning direction and the top to bottomdirection (X direction) as the subscanning direction. An adjacent pixelgroup 4 referred to when determining how the pixels 5 included in asingle pixel block 2 are connected is composed of six pixels 5 that areadjacent to the upper edge and to the left edge of the pixel block 2.During block labeling, the data (referred to as “provisionalidentifiers”, “provisional IDs”, or “provisional labels”) forprovisionally or preliminary identifying the four pixels P included in apixel block 2 is the same, and the four pixels P included in a pixelblock 2 are labeled with the same data in parallel.

As shown in FIGS. 2( a) and 2(b), the four pieces of data (“provisionalidentifiers”, “provisional IDs”, or “provisional labels”) PID(i,j), PID(i,j+1), PID (i+1,j), and PID (i+1,j+1) used to provisionally identifythe four pixels P(i,j), P(i,j+1), P(i+1,j), and P(i+1,j+1) included inthe pixel block 2 are the same. Accordingly, the pixels are labeled inparallel with the same identifier. The provisional identifier of thepixel block 2 is decided by referring to the respective provisionalidentifiers of the six pixels P(i−1,j−1), P(i−1,j), P(i−1,j+1),P(i−1,j+2), P(i,j−1), and P(i+1,j−1) included in the adjacent pixelgroup 4 that have already been labeled with provisional identifiers.This processing is repeated while scanning the entire image 1 in unitsof pixel blocks 2. To simplify the description below, the pixels 5included in a pixel block 2 are referred to as the pixels g0 to g3 inthe order described above and the pixels 5 included in an adjacent pixelgroup 4 are referred to as the pixels r0 to r5 in the order describedabove.

FIGS. 3( a) to 3(d) show examples of where a provisional identifierincluded in the adjacent pixel group 4 is inherited by the pixel block 2based on the states of the pixels in the adjacent pixel group 4 and thestates of the pixels of the pixel 15 block 2. The reference character“X” in FIGS. 3, 4 and 7 is a commonly used cross mark (X-mark). Thecross marked pixels or pixel blocks values can be any of “1” or “0.”Note that in FIGS. 3( a) to 3(d), examples where the provisionalidentifier used to label the pixels 5 of the pixel block 2 is based ononly the state of the upper left pixel g0 of the pixel block 2 areshown. In FIG. 3( a), the pixel g0 of the pixel block 2 is “0”, and itis not possible to decide whether to inherit a provisional identifierbased on the pixel g0 of the pixel block 2 alone. If the other pixels g1and g2 are also “0” and only the lower right pixel is “1”, regardless ofthe state of the adjacent pixel group 4, no provisional identifierincluded in the adjacent pixel group 4 is inheritable and a newprovisional identifier will be assigned to the pixel g3.

In FIG. 3( b), the pixel g0 of the pixel block 2 is “1” and the pixelsr0 to r2, r4, and r5 of the adjacent pixel group 4 are “0”. Accordingly,a provisional identifier that can be inherited by the pixel g0 is notincluded in the adjacent pixel group 4. However, depending on the stateof the pixel r3 of the adjacent pixel group 4 and the state of the pixelg1 in the pixel block 2, there is a possibility of a provisionalidentifier included in the adjacent pixel group 4 being inherited by thepixel block 2. If there is no inheritable identifier, a new provisionalidentifier is assigned to the pixels of the pixel block 2, including thepixel g0.

In the left and right cases shown in FIG. 3( c), the pixel g0 in pixelblock 2 is “1”. In the left case, the pixels r0 and r2 of the adjacentpixel group 4 have been labeled with provisional identifiers. That is,the pixels r0 and r2 of the adjacent pixel group 4 on the left side areboth “1” and since pixels in the adjacent pixel group 4 have alreadybeen labeled with provisional identifiers, a provisional identifier orprovisional identifiers will have already been assigned to the pixels r0and r2. In the right case, a provisional identifier or provisionalidentifiers have been assigned to the pixels r2 and r5 of the adjacentpixel group 4. In addition, since the on-pixels that are “1” in theadjacent pixel group 4 are not consecutive (connected), there is thepossibility that these pixels will have been labeled with differentprovisional identifiers. In these cases, when there are a plurality ofinheritable provisional identifiers for the pixel g0, one of theinheritable provisional identifiers is inherited and connectinginformation for the inherited inheritable provisional identifier and theone or plurality of other inheritable provisional identifiers that havenot been inherited is outputted. That is, when there are a plurality ofinheritable provisional identifiers, one of such inheritable identifiersis inherited as the provisional identifier and other identifier(s)is/are inherited as the connecting information. Accordingly, byreferring to the provisional identifiers and the connecting information,the connected relationships of pixels become clear. Depending on thestates of the other pixels of the pixel block 2 and the other pixels ofthe adjacent pixel group 4, the provisional labels that can be inheritedby the pixel block 2 are not only limited to provisional labels relatedto the pixel g0.

In the left and right cases shown in FIG. 3( d), the pixel g0 of thepixel block 2 is “1”. In the left case, the pixels r0 and r1 of theadjacent pixel group 4 are “1”, the pixels r0 and r1 are connected andtherefore the probability of both pixels r0 and r1 having the sameprovisional identifier is high. In the right case, the pixel r4 of theadjacent pixel group 4 is “1” and has been assigned a provisionalidentifier. In such cases, there is only one inheritable provisionalidentifier for the pixel g0, and therefore such provisional identifieris inherited. However, depending on the other pixels of the pixel block2 and the other pixels of the adjacent pixel group 4, a plurality ofinheritable provisional identifiers may be existed for the pixel block2, and in such case, connecting information is generated.

FIG. 4 shows combinations of the pixels g0 to g3 in the pixel block 2and corresponding combinations of the pixel arrangements of the adjacentpixel group 4 that relate to determining the provisional identifiers ofthe pixel block 2. The combinations #1 to #5 are the cases where one ofthe provisional identifiers assigned to the adjacent pixel group 4 isinherited and assigned to the pixel block 2. Such combinations of theadjacent pixel group 4 shown in FIG. 4 are judged by the logical ORresults, and one of the provisional identifiers have been assigned tothe pixels shown as “1” is inherited as the provisional identifier ofthe pixel block 2 according to the state of the pixels in the pixelblock 2. For example, in the combination #1, if a provisional identifierhas been assigned to any of the pixels P(r0), P(r1), P(r2), P(r4), andP(r5) of the adjacent pixel group 4 and the pixel P(g0) of the pixelblock 2 is “1”, one of the provisional identifiers PID(r0), PID(r1),PID(r2), PID(r4), and PID(r5) of the adjacent pixel group 4 is inheritedas the provisional identifier of the pixel block 2. Out of the pixelsP(g0), P(g1), P(g2), and P(g3) of the pixel block 2, the pixels with thevalue “1” that are subject for grouping are labeled with the provisionalidentifier inherited. That shows the inheritance of provisionalidentifiers shown in FIGS. 3( a) to 3(d).

1.2 Identifying Image Elements by Rough Grouping

The labeling described above is one of that for extracting elementsrespectively composed of strictly consecutively connected pixels.Identifying elements respectively composed of non-consecutively (withinone or a range of few pixels) connecting pixels by rough grouping andextracting such image elements are also effective. Since pixels do notneed to be strictly consecutive for the rough grouping, one ofapplications is that, after an image is converted to data by a scanneror the like, extracting elements that were originally consecutivelyconnected in an image but become non-consecutive by one or a range of afew pixels during the process of converting the image to data.

Compared to the labeling for extracting elements composed of consecutivepixels, it is possible to extract image elements composed of the pixelshaving some relationship at high speed and without degrading the imagedata, and therefore such process can be used as a pre-analysis of animage to the full or real analysis where consecutive elements in theimage are labeled for extracting. One of reference methods includesgenerating a labeled image by applying labeling process to a lowresolution image converted from a high resolution image, provisionallydeciding boundary positions using the labeled image, then generatinganother labeled image by applying labeling process to the original highresolution image on regions in the periphery of the boundaries andfinally deciding the boundary positions. By doing so, it is possible tolimit the region of the high resolution image in which labeling to becarried out. However, the low resolution image data is merely used toprovisionally decide the boundary positions, and since such image datahave low image quality, such data are useless and cannot be used to findthe characteristic values of the image elements. On the other hand, whenapplying the rough grouping for provisionally deciding the boundarypositions, processing speed becomes high without generating data oflower resolution. Since lowering the resolution of the data is notrequired for the rough grouping, the same image data can be used forhigh precision grouping and for finding the characteristic values of theimage elements.

FIGS. 5 and 6 show an example of where rough grouping is carried outusing block labeling. This grouping can identify pixels related to imageelements where the pixels are not necessarily consecutively connected.The pixels 5 for grouping are ON (that have the value “1”) that aresimilar to the above. For rough grouping also, when identifying thepixels 5 disposed in two dimensions, instead of processing the pixels 5one by one, four pixels 5 that are adjacent above, below, left, andright are first processed as a single unit, that is, as a pixel block 2.In addition, in the rough grouping, if at least one of the pixels 5included in the pixel block 2 is ON (that is, the value is “1”), thepixel block 2 is treated as if state of block is ON, and if both pixelblocks 2 that are adjacent, include at least one on-pixel (pixel 5 thatis on) respectively, the common identification information (the sameidentifier, ID, or label value) is assigned to all on-pixels in suchpixel blocks 2.

The pixels 5 included in the pixel block 2 are adjacent to one anotherin two dimensions. This means that if any out of the plurality of pixels5 included in one pixel block 2 is “1”, there is no need to carry out alogic operation for the positional relationships between such pixels.The “1” pixels 5 that are included in the pixel block 2 areconsecutively connected, and are definitely assigned the sameidentifier. In addition, if at least one “1” pixel 5 is included in thepixel block 2, the pixel block 2 is treated as ON. When both pixelblocks 2 adjacent or adjoining each other are ON, all of such pixels 5included in such pixel blocks 2 are assigned the same identifier.Accordingly, by merely calculating the positional relationship of thepixel blocks 2, grouping all of the pixels included in the pixel blocks2 can be performed without calculating the positional relationships ofthe individual pixels 5 included in the pixel blocks 2. This means thata larger number of pixels can be labeled in parallel and that lessprocessing time is spent labeling.

In the rough grouping shown in FIGS. 5 and 6, four pixel blocks 2 thatare adjacent above, below, left, and right are labeled in parallel asone large pixel block 3, that is, the large pixel blocks 3 are the pixelprocessing units for generating a labeled image. The large pixel block 3includes four (i.e., 2×2) pixel blocks 2 that are adjacent to each otherin two dimensions. Accordingly, if any of the plurality of pixel blocks2 included in one large pixel block 3 is ON, further logic operations donot need to be carried out. These pixel blocks 2 should be ON and suchpixels 5 included in such pixel blocks 2 are labeled with the sameidentifier. By carrying out a grouping process with the large pixelblock 3 as a unit, it is possible to process 2×2×4=16 pixels 5 inparallel without a process for logic operations on the relationshipsbetween such sixteen pixels 5.

The pixels 5 included in the large pixel block 3 have a distance-basedrelationship in that they are within a range of two pixel blocks 2, andcan be thought of as being identified as belonging to a group of pixelsthat are linked by such relationship. Also, it can be understood that,when pixels 5 that are ON are included in a large pixel block 3 and inpixel blocks 2 that are adjacent the large pixel block 3, by labelingsuch pixels 5 with the same identifier, pixels that have distance-basedrelationships with a maximum range of three pixel blocks 2 are groupedor segmented.

In the rough grouping, the direction of scanning that has the largepixel blocks 3 as units can be any of up, down, left and right. In thepresent embodiment, as described above, a search is carried out with theleft to right direction (Y direction) for the image 1 shown in FIG. 5 asthe scanning direction and the top to bottom direction (X direction) asthe subscanning direction. Accordingly, the adjacent pixel group 4 forwhich the relationship with one large pixel block 3 is to be determinedis composed of six pixel blocks 2 that are adjoining or adjacent theupper edge and to the left edge of the large pixel block 3.

FIGS. 6( a) and 6(b) show the composition of the pixel blocks 2 includedin the large pixel block 3 and the adjacent pixel group 4. In such blocklabeling, the large pixel block 3 is composed of pixel blocks BL5, BL6,BL8, and BL9 (hereinafter the individual pixel blocks 2 are shown as“BL”) and the provisional identifiers PID5, PID6, PID8, and PID9 of therespective pixel blocks are the same. The provisional identifiers IPD0to PID4 and PID7 respectively assigned to the six small pixel blocks BL0to BL4 and BL7 included in the adjacent pixel group 4 (the group ofadjacent pixel block) are referred to when deciding the provisionalidentifier commonly assigned to the four pixel blocks 2 included in thelarge pixel block 3. The process for labeling process with provisionalidentifiers is repeated while scanning the entire image 1 in units oflarge pixel blocks 3. To label the sixteen pixels Pi0 to Pi15 includedin the large pixel block 3 with a provisional identifier, data of fortypixels in a range of columns Co0 to Co7 of the lines Li0 to Li5,including the adjacent pixel group 4, are inputted in parallel and thesixteen pixels Pi0 to Pi15 are labeled with a provisional identifier inparallel, thereby generating a labeled image that has pixels labeledwith provisional identifiers.

FIGS. 7( a) to 7(d) show an algorithm that carries out labeling based onthe ON/OFF states of the pixel blocks 2 in the adjacent pixel group 4and the ON/OFF states of the pixel blocks 2 in the large pixel block 3so that the large pixel block 3 inherits a provisional identifierincluded in the adjacent pixel group 4 or is assigned a new provisionalidentifier. In FIG. 7( a), all of the pixel blocks 2 included in thelarge pixel block 3 are “0”. That is, the large pixel block 3 does notinclude any pixels 5 that are ON and subjects for grouping, andtherefore the labeling process that assigns a provisional identifier isnot carried out (NOP).

In FIG. 7( b), all of the pixel blocks 2 included in the adjacent pixelgroup 4 are zero and on-pixels are included in the large pixel block 3.In this case, the adjacent pixel group 4 does not include any ON pixels5 that are subject for grouping and there are no inheritable provisionalidentifiers. For this reason, a new provisional identifier is assignedto all of such pixels 5 of the pixel blocks 2 included in the largepixel block 3. That is, the pixels 5 that are ON included in the largepixel block 3 are commonly labeled with a new provisional identifier.

In FIG. 7( c), pixel blocks 2 that are ON but are not adjacent areincluded in the adjacent pixel group 4 and on-pixels are included in thelarge pixel block 3. In the adjacent pixel group 4, there is thepossibility that pixels have been labeled with different provisionalidentifiers in pixel block 2 units. Accordingly, the pixel blocks 2 inthe large pixel block 3 inherit one of the plurality of provisionalidentifiers present in the adjacent pixel group 4 by labeling suchpixels 5 in the large pixel block 3 with the inherited provisionalidentifier. In addition, it is determined that such pixel blocks 2 ofthe adjacent pixel group 4 are included in the same group via the largepixel block 3. Accordingly, when a new connecting relationship is knownfor the provisional identifiers of such pixel blocks 2 in the adjacentpixel group 4, connecting information of the provisional identifiersthat are in connecting relationship is output.

In FIG. 7( d), pixel blocks 2 that are ON and are also adjacent areincluded in the adjacent pixel group 4 and on-pixels are included in thelarge pixel block 3. Accordingly, the provisional identifier of theadjacent pixel group 4 is commonly assigned to such pixels 5 of thepixel blocks 2 in the large pixel block 3. Since adjacent pixel blocks 2that are ON are present in the adjacent pixel group 4, the sameprovisional identifier will have already been assigned to such pixelblocks 2, and a new connecting relationship will not produced.

With the algorithm shown in FIG. 7, even if pixel blocks 2 are notadjacent, by way of the large pixel blocks 3, such pixel blocks 2 can beassigned the same provisional identifier to group such blocks togetheras belonging to the same group. Accordingly, the same provisionalidentifier is assigned to such pixels 5 included in a range of a maximumof three small pixel blocks 2. In place of the algorithm shown in FIG.7, it is possible to use an algorithm that assigns the same provisionalidentifier to only pixel blocks 2 that are completely adjacent oradjoining each other. Such algorithm is the similar as that describedabove with reference to FIGS. 3 and 4, and assigns the same provisionalidentifier to such pixels 5 included in a maximum range of two pixelblocks 2.

In the algorithm shown in FIG. 7, the condition of a large pixel block 3is only whether a pixel 5 that is ON is included in the large pixelblock 3. Accordingly, determining the state of the large pixel block 3by calculating a logical OR for the sixteen pixels 5 included in thelarge pixel block 3 is effective. The states of the adjacent pixel group4 depend on the pixel blocks 2 that are ON and included in the adjacentpixel group 4, and the states of the individual pixel blocks 2 can bedetermined by calculating a logical OR for the four pixels 5 included ineach pixel block 2. Accordingly, by using hardware with sufficientperformance or functioning to calculate a logical OR for a plurality ofpixel data in parallel, it is possible to carry out the labeling withprovisional identifiers by pipeline processing.

In this way, block labeling is also effective for roughly grouping alarge number of pixels that compose an image. If the process forgrouping or segmenting consecutively connected pixels is called labelingor fine grain labeling, the process described above can be called roughlabeling (or coarse grain labeling). For rough labeling, the sameidentifier (label) is assigned even if pixels are some distance apart,namely such pixels do not need to be strictly adjoining, thereby makingit possible to identify elements composed by such pixels in an image.This means that low pass filtering that is a former process and aconnecting process that is a latter process are executed at the sametime as the labeling process. By carrying out rough labeling, the sizeof the block to be processed is increased and the process that assignsprovisional labels can be accelerated. Since the number of provisionallabels falls, number of provisional labels to be combined is alsoreduced, generating a merging table by sorting the connectingrelationships is accelerated, and the process of assigning real labelsis also accelerated.

Accordingly, for a high-resolution image, grouping becomes possible thatgroups pixels that are included in a high-resolution image at high speedwithout having to convert the image to a low-resolution image. Providingsoftware and an image processing apparatus becomes possible that canidentify boundaries and the like of an image at high speed, and inaddition, since the resolution of the image can be maintained for roughprocess, it is possible to obtain characteristic values of imageelements with high precision.

2. Image Processing with Block Labeling

FIG. 8 is a flowchart showing one example of processing that analyzes animage using block labeling. In this flowchart, the principal inputs andoutputs of data are shown by dot-dash lines. The image processing 10generates a labeled image and calculates characteristic values of imageelements that have been distinguished from the labeled image. The imageprocessing 10 includes process of generating the labeled image 25, thegenerating the labeled image including a first stage 11 that scans theimage and attaches provisional identification information (“provisionalidentifiers”, “provisional IDs”, or “provisional labels”) to groups ofpixels that compose image elements, and a second stage 12 that relabelsthe groups of pixels with the same real identification information(“real identifiers”, “real IDs”, or “real labels”) so as to merge thegroups of pixels that have been assigned different provisionalidentifiers but compose the same image elements. As described above, thepixels that are not consecutively connected and are in a predeterminedrelationship can be grouped by the block labeling as well as the pixelsthat are consecutively connected. Accordingly, the image elements thatcan be distinguished in the image processing 10 are not limited to imageelements composed of consecutively connected pixels.

The following description will focus on an image processing method thatidentifies and analyzes image elements composed of pixels that have beenroughly grouped using block labeling. The image processing 10 alsoincludes an analysis stage 13 that extracts characteristic values ofimage elements composed of pixels that have been grouped together. Toextract characteristic values not just for binary images but also forimages expressed by multivalues or multiple shades (grayscale images),the image processing 10 further includes a process 14 that calculatesblock characteristic values of pixel blocks composed of multivaluepixels in parallel with the first stage 11 that labeling withprovisional identifiers.

The first stage 11 of labeling with provisional identifiers includes thestep of inputting 100 that obtains, from the pixel data 29 includingpixels that construct the image, sixteen pieces of pixel data includedin the large pixel block 3 and twenty-four pieces of pixel data of theadjacent pixel group 4 adjacent to the large pixel block 3 to provide tothe step of labeling 200 described below. The step of labeling 200included in the first stage 11 can label the sixteen pixels 5 includedin the large pixel block 3 with the same provisional identifiers.

In the step of inputting 100, in step 101, the data of the pixels 5included in the large pixel block 3 are inputted from the pixel datafile 29. In step 102, if unprocessed data are inputted from the pixeldata that constitutes the image 1, in step 103 the multivalue pixel data5 obtained from the pixel data file 29 are binarized. If the pixel dataof the file 29 have already been binarized, this step is unnecessary.Data on the pixels 5 of the adjacent pixel group 4 that have beenalready labeled with provisional identifiers and temporarily stored in abuffer (buffer memory) 28 and data on the provisional identifiersassigned to such pixels 5 are obtained in step 104.

In the step of labeling 200, in step 201, a logic operation is carriedout for judging the conditions or states of the large pixel block 3 andthe adjacent pixel group 4 and in step 202, it is determined whether anyinheritable provisional identifiers are existed. The algorithm forinheriting provisional identifiers was described above with reference toFIGS. 7( a) to 7(d). When the adjacent pixel group 4 includes only oneinheritable provisional identifier (condition d1), in step 205, theprovisional identifier is inherited, and the pixels 5 of the large pixelblock 3 are labeled with such the same provisional identifier and areoutputted in the large pixel block 3 unit to a provisionally labeledimage file 27. In addition, information on the provisional identifierincluded in the adjacent pixel group 4 that will be required in laterprocessing of the large pixel block 3 is temporarily stored in pixelblock 2 units in the buffer memory 28 that can be accessed at highspeed.

When the adjacent pixel group 4 includes a plurality of provisionalidentifiers that can be inherited or should be inherited (condition d2),in step 203, connecting information for the plurality of provisionalidentifiers is recorded. That is, connecting information for theprovisional identifier inherited by the pixels 5 of the large pixelblock 3 and the other identifiers that are not inherited is outputted toa connecting information file 26. In step 205, the pixels 5 of the largepixel block 3 are labeled with the inherited provisional identifier andare outputted to the provisionally labeled image file 27. When theadjacent pixel group 4 does not include any inheritable provisionalidentifiers (condition d3), in step 204, a new provisional identifier isgenerated and in step 205, the pixels 5 of the large pixel block 3 arelabeled with the new provisional identifier and are outputted to theprovisionally labeled image file 27. By doing so, a provisionallylabeled image in which the pixels that constitute the input image havebeen labeled with provisional identifiers is generated.

In the first stage 11 of labeling using the provisional identifiers, inthe step of inputting 100, data on forty pixels Pi included in the largepixel block 3 and the adjacent pixel group 4 are read in parallel. Next,in the step of labeling 200, processes of labeling, with provisionalidentifiers, the pixels to be grouped (in the present embodiment, pixelsthat are ON (i.e., pixels with the value “1”)) out of the sixteen pixelsPi included in the large pixel block 3 are carried out in parallel. Thestep of inputting 100 and the step of labeling 200 can be implemented onhardware as a series of processes and executed by pipeline processing.In addition, in the step of labeling 200, the step 201 that decodes andoperates the inputted forty pixels Pi to judge inheritance and the step205 that labels the pixels with the provisional identifiers decided bythe step 201 can be implemented on hardware so that such steps areexecuted by pipeline processing. Accordingly, the processing of thefirst stage 11 that labels the sixteen pixels 5 included in the largepixel block 3 with provisional identifiers can be executed ineffectively one clock cycle.

The step 203 that records the connecting information and the step 204that selects a new provisional identifier also use the result ofdecoding the large pixel block 3 and the adjacent pixel group 4. Theprocessing of steps 203 and 204 can be implemented on hardware asincluded in the first stage 11 and the processing is executed inparallel with the processing of the step 201 that operate an inheritanceand of the step 205 of labeling. Including these steps, the processingof the first stage 11 is executed without breakdown and/or delays in thepipeline for reading and labeling sixteen pixels.

In the image processing 10, in the analyzing process 14 carried out inparallel to the first stage 11 that assigns the provisional identifiers,the multivalue data of the pixels 5 included in the large pixel block 3under the labeling with the provisional identifiers is analyzed and graylevel information is calculated in parts corresponding to the largepixel blocks 3. By the process, the gray level information is compressedas block characteristic values (to 1/16 the size in the presentembodiment) corresponding to the large pixel blocks 3 and are outputtedto a block characteristic value file 22. Since the sixteen pixels 5included in the large pixel block 3 are labeled with the sameprovisional identifier, such pixels are later labeled with the same realidentifier and constitute the same image element. Accordingly, inprocess 14, it is effective to find gray-level information, such asmaximum and minimum density values, an average value, and other valuesin advance in large pixel block 3 units from multivalue data (such as“shade data” or “grayscale data”) of the sixteen pixels 5 included inthe large pixel block 3. After this, by calculating totals in largepixel block 3 units for the block characteristic values, for example thegray level information, based on the connecting information of theprovisional identifiers, it is possible to find the gray levelinformation of the respective image elements and to reduce theprocessing time taken to analyze the gray level information.

In addition, in the first stage 11 of labeling with the provisionalidentifiers, the pixels 5 included in the large pixel block 3 areinputted from the pixel data file 29. For this reason, by finding thegray level information of the large pixel block 3 in parallel with thefirst stage 11, it is possible to omit a process that accesses the pixeldata file 29 to calculate the gray level information, which also makesit possible to reduce the processing time taken to analyze the graylevel information.

When the first stage 11 is completed, in step 15, a merging table 23 isgenerated from the connecting information stored in the connectinginformation file 26. In step 203, when pixels 5 that have been labeledwith different provisional identifiers are included in the adjacentpixel group 4, pairs of the provisional identifier inherited by thepixels of the large pixel block 3 and the non-inherited provisionalidentifier(s) are recorded in the connecting information file 26. Theinherited provisional identifier and non-inherited provisionalidentifier(s) are identification information that show the same group(image element). For this reason, in the second stage 12, the pixels 5that have been labeled with such provisional identifiers are relabeledwith an identifier (a real identifier) showing that the pixels 5ultimately belong to the same group. It is necessary to merge, integrateor combine the inherited provisional identifiers and the non-inheritedprovisional identifiers, and for this reason, in step 15, the mergingtable 23 is generated.

In step 15, based on the connecting information file 26 for theprovisional identifiers, the same real identifier (real label) isassigned to provisional identifiers that have been assigned to pixelsbelonging to the same group, and the merging table 23 showingcorrespondence between the provisional identifiers and the realidentifier is generated. With the merging table 23, by using aprovisional identifier as an address, for example, the correspondingreal identifier can be read. Therefore by referring to the merging table23 with the provisional identifier as an address, it is possible toconvert the provisional identifier to a real identifier. If someprovisional identifiers are connected, when extracting image elementscomposed by pixels connected, such connecting information show thatpixels that are labeled with the some provisional identifiers areconnected. In the rough grouping, the connecting of a plurality ofprovisional identifiers does not mean that pixels labeled with the someprovisional identifiers are necessarily consecutively connected.However, such pixels are related within a predetermined range.

Next, in the second stage 12, while referring to the merging table 23,the pixel data stored in the provisionally labeled image file 27 arelabeled with real identifiers, thereby generating a labeled image(real-labeled data) that is outputted as the labeled image file 25. Theprovisionally labeled image may also be recorded in bitmap format. Byrecording in units of pixel blocks 2 with the same provisionalidentifiers and also in units of large pixel blocks 3, it is possible toreduce the amount of used memory, and in the second stage 12, it becomeseasy to read the pixel data in units of large pixel blocks 3. In thesecond stage 12, in step 121 the pixel data included in theprovisionally labeled image file 27 is inputted in parallel in largepixel block 3 units. In step 122, when data not relabeled are inputtedfrom the provisionally labeled image file 27, in step 123, the mergingtable 23 is referred to and the provisional identifier of the largepixel block 3 is converted to a real identifier, and the pixels 5included in the large pixel block 3 are labeled with the same realidentifier in parallel. Labeled data that has been labeled with the realidentifiers to identify independent image elements composed of pixels 5in a predetermined relationship is generated and outputted to thelabeled image file 25. In step 123 of labeling with the realidentifiers, pixels for grouping included in a large pixel block 3 arelabeled in parallel in large pixel block 3 units with the same realidentifier.

In the image processing 10, when the second stage 12 has been completed,the analysis stage 13 is executed. In the analysis stage 13, in step131, analysis is carried out in large pixel block 3 units and the blockcharacteristic values of the large pixel blocks 3 are calculated. Next,in a step 132, a process that totals the block characteristic values ofthe large pixel blocks 3 that have the same real identifier isrepeatedly carried out to calculate a characteristic value for eachimage element. Characteristic values that can be calculated from binarypixels or binary data can be calculated in pixel block or large pixelblock units from the provisionally labeled image file 27 in whichbinarized pixels have been labeled with provisional identifiers.Regarding the gray level information, the block characteristic values oflarge pixel blocks 3 are obtained as described above in stage 14.Accordingly, by calculating a total in step 133, it is possible tocalculate characteristic values relating to the gray level of each imageelement. These characteristic values include information such as area,center of gravity, and height/width dimensions.

In the analysis stage 13, instead of calculating the characteristicvalues for each image element based on the labeled image 25 that hasbeen labeled with real identifiers, it is possible to refer to themerging table 23 and total the block characteristic values for eachimage element. Accordingly, if there are sufficient hardware resources,it is possible to configure hardware so that the analysis stage 13 isexecuted in parallel with the second stage 12.

3. Image Processing System

In the image processing 10 described above, the first stage 11 oflabeling with the provisional identifiers and the second stage 12 oflabeling with the real identifiers are executed in that order. For thesame image, such processes (steps) do not overlap. As described above,the analysis stage 13 may be executed after or in parallel with thesecond stage 12. For example, after the step 15 of generating themerging table 23 has been completed, the second stage 12 of labelingwith the real identifiers and the analysis stage 13 can be carried outin parallel.

The execution timings of the first stage 11 and the second stage 12 donot overlap. This means that by executing the image processing 10 byconfiguring a circuit for executing the first stage 11 and then acircuit for executing the second stage 12 on reconfigurable hardware,efficient use can be made of hardware resources.

The image processing 10 can process a large amount of pixel data inparallel to reduce the processing time. By implementing the imageprocessing 10 in a processor equipped with a processing region thatincludes a plurality of processing elements and in which a plurality ofdata paths that operate in parallel are configured by the plurality ofprocessing elements, it is possible to make the most of thecharacteristics of the image processing 10 and thereby reduce theprocessing time. The processing elements should preferably include acertain level of arithmetic logic processing and should preferably beincluded in a reconfigurable integrated circuit device.

A processing device 30 shown in FIG. 9 is one example of reconfigurablehardware and includes a region where circuits can be dynamicallyreconfigured. The processing device 30 includes a matrix region(processing region) 31 in which processing elements (hereinafterreferred to as “EXE”) 32 equipped with a certain level of arithmeticlogic processing, such as an ALU, are connected to configure variousdata paths. The processing device 30 also includes a controller 33 thatcontrols connections between the EXEs 32 of the matrix 31 to dynamicallyconfigure data paths, a RAM 34 in which hardware information(configuration information) of the data paths to be configured in thematrix 31 is recorded, and a buffer 35 in which data to be processed bythe circuits of the matrix 31 is temporarily recorded. The processingdevice 30 also includes an interface for inputting and outputting datainto and out of an external memory 36.

The processing device configures data paths that operate in parallel byconnecting a plurality of EXEs 32 and it is a hardware resource that issuited to the image processing 10, i.e., to processing a plurality ofpixel data in parallel. By reconfiguring the connections of the EXEs 32of the matrix region (hereinafter, simply “matrix”) 31 of the processingdevice 30 so as to execute the stages 11 to 13 of the image processing10 in order, it is possible to use the matrix region as a dedicatedprocessing system for executing the image processing 10. An imageprocessing system 50 that executes the image processing 10 using theprocessing device 30 is described below. Note that, in the processingdevice 30, it is possible to execute not only image processing relatingto labeling but also other processing simultaneously if the hardwareresources such as the EXEs 32 of the matrix 31 are sufficient to suchmulti processing.

FIGS. 10( a) to (c) show how the matrix 31 that is the processing regionis reconfigured so that the processing device 30 functions for the imageprocessing system 50. To have the processing device 30 function for theimage processing system 50, in this example three types of configurationinformation 51 to 53 are prepared in advance and stored in theconfiguration RAM 34 of the processing device 30. The configuration ofthe matrix 31 is changed at appropriate timing by the controller 33 toexecute the image processing 10. FIG. 10( a) shows the matrix 31 havingbeen reconfigured according to the first configuration information 51 soas to execute in parallel the first stage 11 and the process 14 wheremultivalue image data is analyzed in large pixel block 3 units. FIG. 10(b) shows the matrix 31 having been reconfigured according to the secondconfiguration information 52 so as to execute the process that generatesthe merging table. FIG. 10( c) shows the matrix 31 having beenreconfigured according to the third configuration information 53 so asto execute the second stage 12 and the analysis stage 13 in parallel.

As shown in FIG. 10( a), by the first configuration information 51, aninterface 54 and a labeling processor (labeling engine) 55 areconfigured in the matrix region 31 of the processing device 30, theinterface 54 including a configuration for executing the step ofinputting 100 of the first stage 11 and the labeling engine 55 includinga configuration for executing the step of labeling 200. In addition, ananalysis processor (analysis engine or second processor) 56 including aconfiguration for executing the process 14 that analyzes multivaluepixel data and a peripheral circuit 57 including a circuit for supplyingdata from the interface 54 to the labeling processor 55 and the analysisprocessor 56 are configured in the matrix region 31 by the firstconfiguration information 51. The interface 54 includes a function forinputting the pixel data included in the large pixel block 3 in paralleland a function for inputting data on the provisional identifiers of theadjacent pixel group 4. The labeling processor 55 includes a function 55a that calculates and determines inheritance of provisional identifiers,a function 55 b that labels using the provisional identifiers, afunction 55 c that outputs the connecting information on the inheritedprovisional identifier and the non-inherited provisional identifiers,and a function 55 d for generating a new provisional identifier. Thefunction 55 b for labeling with the provisional identifiers assigns aninherited provisional identifier or a new provisional identifier as thesame or common provisional identifier in parallel to all of the ONpixels 5 that are subjects for grouping and are included in the largepixel block 3.

FIG. 11 shows an overview of the circuits configured in the matrix 31 bythe first configuration information 51 in more detail. The interface 54loads the pixel data included in the large pixel block 3 from the pixeldata file 29 in the external memory 36, binarizes the pixel data using abinarizing circuit 61, and supplies the binarized data to the labelingprocessor 55. At the same time, the multivalue pixel data is supplied tothe analysis processor 56. The provisional identifiers (provisional IDs)of the adjacent pixel group 4 are obtained from the buffer 28 andsupplied to the labeling processor 55. The labeling processor 55 isequipped with a logic circuit 65 that calculates a logical OR for datasupplied from the interface 54, a lookup table (LUT) 66 that determinesfrom the results of the logical OR whether there are any provisional IDsto be inherited, a selector 67 that selects a provisional ID, and aselector 68 that selects connecting information.

The logic circuit 65 generates an address 79 including ten values bycarrying out logical OR operations on a total of ten pixel blocks 2 (BL0to BL9 in FIG. 6) corresponding to a large pixel block 3 and theadjacent pixel blocks 4. The LUT 66 uses this value 79 as an addressinput and outputs a microcode stored at that address as an ID controlsignal 71. Various logic circuits such as the selectors 67 and 68 arecontrolled using this microcode 71.

The data generating circuit 69 can labels the sixteen pixels 5 includedin the large pixel block 3 in parallel with a provisional ID. In thisexample, the data generating circuit 69 gathers sixteen pieces of binarypixel data supplied from the interface circuit 54 and the selectedprovisional ID 72 to output the one word (32 bits) of block pixel data73. That is, the block pixel data 73 includes an ID 73 d and pixel data73 p for sixteen pixels. The labeling of the sixteen pixel data includedin the large pixel block 3 is collectively carried out in parallel asone word of data. The provisionally labeled image data outputted to theprovisionally labeled image file 27 is composed of such block pixel data73.

FIG. 12 shows an overall circuit configuration in the labeling processor55 for generating and outputting block pixel data 73 from the suppliedpixel data. First, the interface 54 uses a shift register and maskcircuit to cut out the pixel data included in the large pixel block 3and the adjacent pixel group 4 (the group of adjacent pixel blocks) fromthe pixel data 29 that has been stored from the external memory 36 in aline buffer 35. As one example, pixel data of the lines Li0 to Li5 andcolumns Co0 to Co7 shown in FIGS. 5 and 6 is loaded. If sufficient buswidth can be reserved, 40 bits of pixel data for 40 dots can be read outin one clock (cycle).

The logic circuit 65 of the labeling processor 55 calculates a logicalOR for the pixel data 5 of the 0^(th) line Li0 and the first line Li1using an OR circuit 65 a and judges whether the blocks BL0 to BL3 areON, that is, whether the respective blocks include at least oneon-pixel. In the same way, a logical OR is calculated for the pixel data5 of the 2^(nd) line Li2 and the 3^(rd) line Li3 using an OR circuit 65b to judge whether the blocks BL4 to BL6 are ON. A logical OR is alsocalculated for the pixel data 5 of the 4^(th) line Li4 and the 5^(th)line Li5 using an OR circuit 65 c to judge whether the blocks BL7 to BL9are ON.

The states of the adjacent pixel group 4 and the large pixel block 3 canbe determined from the calculation results of the OR circuits 65 a, 65b, and 65 c. To do so, a logical OR is also calculated on the outputs ofthe OR circuits 65 a, 65 b, and 65 c by the OR circuit 65 d to generatea logical OR result for the ten pixel blocks BL0 to BL9 as a 10-bitaddress input 79 which is supplied to the LUT 66. By the address, asuitable microcode is outputted from the LUT 66 as the ID control signal71. The LUT 66 can be realized using RAM elements provided in advance inthe matrix region 31.

The circuit having such configuration performs a series of processesthat loads the pixels 5, calculates logical ORs in order and outputs theID control signal 71 sequentially with no backtracking. Accordingly, byconfiguring data paths for many parallel processes using the largenumber of elements 32 disposed in the reconfigurable matrix 31,processes on pixel data related to one or a plurality of large pixelblocks 3 can be carried out in parallel and such processes becomessubjected to be pipeline processing. The provisional IDs for at leastone large pixel block 3, that is, at least sixteen pixels can bedetermined in effectively one clock (cycle).

The data generating circuit 69 generates one word (i.e., 32 bits) ofblock pixel data 73, which includes information on the sixteen pixelsincluded in one large pixel block 3 and provisional ID information thathas been commonly assigned to the sixteen pixels, and outputs the blockpixel data 73 to the provisionally labeled image file 27 asprovisionally labeled image data. In this block pixel data 73, it ispossible to also include position information of the large pixel block3, a characteristic value of the large pixel block 3 that has beencalculated from information on sixteen pixels, and the like.

To generate the block pixel data 73, it is necessary to supply the datagenerating circuit 69 with the data of the sixteen pixels included inthe large pixel block 3 and data 72 on the provisional ID assigned tosuch pixels. To supply the data 72 on the provisional ID of the largepixel block 3 to the data generating circuit 69 according to the IDcontrol signal 71 of the LUT 66, a certain amount of calculation time isrequired following the input of the pixel data of the large pixel block3. By supplying the data of the sixteen pixels loaded by the inputinterface 54 to the data generating circuit 69 via a suitable delaycircuit or a pipeline register, the data can be supplied to the datagenerating circuit 69 in synchronization with the data 72 on theprovisional ID of the large pixel block 3. Accordingly, in the labelingprocessor 55, after the pixel data of the large pixel block 3 has beenloaded from the line buffer 35, the processing as far as the labelingthe pixel data with a provisional ID can be carried out by pipelineprocessing.

This means that in the image processing system 50, the provisional ID isdecided for at least one large pixel block 3, that is, at least sixteenpixels and provisionally labeled image data that has been labeled withsuch provisional ID can be outputted in effectively one clock cycle.Accordingly, the image processing system 50 can group at least sixteenpixels in one cycle, and compared to a process that carries out groupingin single pixel units, image processing can be carried out over tentimes faster. Also, pixel data 73 p of the original resolution is storedin the grouped block pixel data 73, and therefore there is no fall inthe resolution of the analyzed image.

FIG. 13 shows the overall configuration of a processor 56 that extractscharacteristic values in large pixel block 3 units. To the analysisprocessor 56, the interface 54 supplies the original data, that is,grayscale (multivalue) pixel data for sixteen pixels included in onelarge pixel block 3 cut out from the line buffer 35. Processing units 62having threshold values judges whether the respective pixel data are tobe compared for setting a maximum or minimum of the gray level. Theselectors 63 a and 63 b respectively select (calculate) a maximum valueand a minimum value for the data on the sixteen pixels that have beenprocessed with the threshold and the results of such calculations arepacked into one word of gray level data 74 by a shift/OR circuit 63 c.If there is no error for the calculation of the maximum value andminimum value, the gray level data 74 passes a gate circuit 63 d and isoutputted to the block characteristic value file 22.

FIG. 14 shows a circuit configuration in the processing unit 62 havingthreshold values for carrying out an operation on one pixel with thethreshold values. Pixel data 29 p for one pixel is compared with a firstthreshold 62 b by a comparator 62 a and the pixel data 29 p is judged tobe significant if the pixel data 29 p is larger than the first threshold62 b. As a result, a carry 62 x is asserted and the pixel data 29 p isoutputted by the selector 62 e as data to be compared with the maximumvalue. When the pixel data 29 p falls below the first threshold 62 b,“0” is outputted from the selector 62 e and the pixel data 29 p isignored as a maximum value. The pixel data 29 p is also compared with asecond threshold 62 d by a comparator 62 c and is judged to besignificant if the pixel data 29 p is smaller than the second threshold62 d. As a result, a carry 62 y is asserted and the pixel data 29 p isoutputted by the selector 62 f as data to be compared with the minimumvalue. When the pixel data 29 p is above the second threshold 62 b, “FF”is outputted from the selector 62 f and the pixel data 29 p is ignoredas a minimum value. A logical OR is calculated by a circuit 62 g for thecarries 62 x and 62 y that show the comparison results and a logical ORthat includes the comparison results for other pixels is calculated by acircuit 62 h.

If, as a result, one of the pixel data 29 p is outside the range of thefirst threshold value 62 b and the second threshold value 62 d, suchpixel data 29 p is outputted as significant gray level information. Onof examples of this process is determining whether defects are present,and if the gray level data for all pixels is within the range of thefirst threshold value 62 b and the second threshold value 62 d, it isdetermined that there are no defects in the range of the large pixelblock 3 being analyzed and gray level information is not outputted.

In the same way as the labeling processor 55, the analysis processor 56outputs the gray level information 74 in units of large pixel blocks 3.As shown in FIG. 15, the block characteristic data 74 that is gray levelinformation in block units one-to-one corresponds to the block pixeldata 73. Accordingly, by calculating totals based on the provisionalidentifiers (provisional IDs) and the merging table 23 at a lager stage,it is possible to obtain characteristic values (gray level information)for each image element.

At a time after the first stage 11 has been completed, as shown in FIG.10( b), the matrix 31 is reconfigured using the second configurationinformation 52 so as to generate the merging table. The provisionalidentifiers inherited by the pixels of the large pixel block 3 and thenon-inherited provisional identifiers paired with such provisionalidentifiers are recorded in the connecting information file 26. At thefollowing stage before generating the labeled image, the merging table23 is generated by assigning the same real identifiers (real IDs) to thepairs of one or a plurality of provisional identifiers in a connectingrelationship.

The algorithm that generates the merging table 23 from the connectinginformation file 26 is as follows. In the connecting information file26, a plurality of entries that show the connection of two provisionalIDs are recorded. In the merging table 23, with a provisional ID as anaddress, the real label corresponding to the provisional identifiershould be obtained.

-   Step h1: If the provisional IDs in the n^(th) entry in the    connecting information file 26 are assumed to be “a” and “b”, the    n^(th) entry is stored as a group queue.-   Step h2: The top entry of the group queue, for example the pair “a”    and “b”, is stored in a comparison register.-   Step h3: The values from the n^(th) value onward are read from the    connecting information file 26 and compared with the values “a” and    “b” in the comparison register.-   Step h4: An entry where at least one value matches with the “a” or    “b” is added to the group queue.-   Step h5: When the end of the connecting information file 26 is    reached, the next entry is read from the group queue, is stored in    the comparison register, and the same operation is carried out.-   Step h6: When the end of the group queue is reached, all provisional    IDs entered in the group queue are assigned the same real    identifier.

As described above, information stored in the merging table 23 for onereal ID is obtained, thereby completing the group for that real ID.Next, the n+1^(th) entry is read from the connecting information file 26and the same operation is carried out. However, connecting informationthat has already been stored in the group queue once is not stored inthe group queue again. After the operation described above is completed,if there are provisional IDs that are yet to be assigned real IDs,unique real IDs are respectively assigned to such provisional IDs. Bycarrying out the operation described above, the merging table 23 issuccessfully generated. The second configuration information 52configures data paths for carrying out the algorithm described above inthe matrix region 31.

At a time after the merging table 23 has been generated, as shown inFIG. 10( c), the matrix 31 is reconfigured by the third configurationinformation 53 so as to execute the second stage 12. At that time, thematrix 31 is also configured to execute the analysis stage 13 by thethird configuration information 53. To execute the second stage 12, thethird configuration information 53 configures an interface 59 thatinputs the block pixel data 73 including the provisional IDs 73 d andthe pixel data 73 p from the provisionally labeled image file 27 and alabeling processor (labeling engine) 60 that relabels the provisionalIDs with the real IDs. Also, to execute the analysis stage 13, the thirdconfiguration information 53 configures an analysis processor 80(analysis engine or “first processor”) that includes a circuit 81 thatdecodes the block pixel data 73 to calculate characteristic values inlarge pixel block 3 units and a circuit 82 that totals suchcharacteristic values in block units based on the merging table 23 andthereby calculates a characteristic value for each image element.

FIG. 16 shows an example circuit of the labeling processor 60 that readsthe block pixel data 73 and refers to the merging table 23 to label withreal identifiers (real IDs or real labels) in large pixel block 3 units.First, the interface circuit 59 accesses the provisionally labeled imagefile 27 and obtains the block pixel data 73. The block pixel data 73includes pixel data 73 p for sixteen pixels that constitute a largepixel block 3 and such pixel data is inputted in parallel. In thelabeling processor 59 b for the real identifiers, the merging table 23is accessed with the provisional ID 73 d of the block pixel data 73 asan address to obtain the real ID. Based on the pixel data for sixteenpixels in the block pixel data 73, the elements 32 of the matrix 31 areused as selectors that operate in parallel so that the ON (“1”) pixelsthat are to be grouped together are assigned the real ID, other pixelsare set at “0”, and the labeled pixels are outputted to the labeledimage file 25.

The labeling processor 60 can also output block pixel data produced byrewriting the ID values 73 d of the block pixel data 73 from provisionalIDs to real IDs as the labeled image data. In this case also, the data73 p of sixteen pixels is collectively labeled in parallel with the samereal ID.

FIG. 17 shows an example circuit of the analysis processor 80. Logicthat finds a maximum value in the Y coordinate direction is implementedin this circuit 80. The circuit 80 includes a first circuit 81 thatfinds characteristic amounts (maximum values) of the respective largepixel blocks 3 using a decoder and a second circuit 82 that calculatestotals of the characteristic amounts using the real IDs and findsmaximum values of pixels grouped by the real IDs. The first circuit 81includes a decoder 83 that converts the data 73 p of sixteen pixels inthe block pixel data 73 to control data and a selector 84 that findscharacteristic values, that is, maximum values in the Y coordinatedirection in large pixel block 3 units from the control data. The secondcircuit 82 includes a Y-max table I/F 86, which converts the provisionalID 73 d of the block pixel data 73 to a real ID using the merging table23 and accesses the Y-Max table 85 with the real ID as an address, and aselector 87 that selects a maximum value. The selector 87 selects, amongthe inputs of a Y-coordinate maximum value obtained via the Y-Max tableI/F 86 from the table 85 by the real ID and a Y coordinate obtained bythe selector 84, the new maximum value. In addition, the selector 87outputs the new maximum value via the I/F 86 to the Y-Max table 85 toupdate the maximum value.

By the analysis processor 80, it is possible to find the width in the Ydirection of the image element composed of the pixel groups that havebeen segmented. In the same way, a variety of characteristic amountssuch as a minimum value in the Y coordinate direction and the maximumvalue and minimum value in the X coordinate direction can be found.Since it is possible to calculate the characteristic amounts in units oflarge pixel blocks 3 that are composed of sixteen pixels, the processingtime required to calculate the characteristic amounts can be reduced.

The analysis processor 80 also includes a circuit 89 that reads thefollowing block pixel data 73, compares the real IDs via the mergingtable 23 and when the real IDs are the same, finds a maximum value byincluding the following block pixel data 73 before the data is writteninto the table 85. This circuit 89 can reduce the processing time whenblock pixel data 73 with the same ID is consecutive. Since the analysisprocessor 80 carries out a read-modify-write process on the Y-Max table85, a function for a situation where the same real ID is consecutivelyinputted is required in order to not increase the latency of thepipeline. In addition to the circuit 89 in FIG. 17, by reading inadvance and comparing the following block pixel data 73, it is possibleto reduce the latency of the feedback path from five cycles to threecycles.

The image processing method 10 and image processing device 50 describedabove can group pixels, when such pixels are not strictly adjoining,according to desired rules. A processing method and processing devicefor labeling pixels consecutively connected are also be provided withsubstantially the same configuration using the logic for assigning theprovisional identifiers described with reference to FIGS. 3 and 4.

In addition, although an example where a two-dimensional binary image isanalyzed has been described above, the scope of the present invention isnot limited to. Although the small pixel blocks 2 that are the basicunits are composed of four pixels that are adjacent to one another, whengrouping together pixels that are related in a wider range, the pixelblocks used as basic units may be composed of five or more pixels.Similarly, although the large pixel blocks 3 are composed of four pixelblocks 2 that are adjacent to one another, when grouping together pixelsthat are related in a wider range, the large pixel block may be composedof five or more pixel blocks 2. Also, the binarization of the pixels isnot limited to monochrome images and it is possible to binarize theseparate color components of a color image. In addition, the presentinvention is not limited to processing two-dimensional images and can beapplied to block labeling of three-dimensional images and in such case,as described above, the pixel blocks that are the basic units arecomposed of eight pixels that are adjacent to one another.

1. A method of generating a labeled image, including the steps of:inputting a pixel block, which includes a plurality of pixels that areadjacent to one another in more than one dimension, as a single unitfrom data including pixels for forming an image; and labeling, based onbinarized pixels, all on-pixels or all off-pixels that are subjects forgrouping and are included in the pixel block with common identificationinformation, wherein the method further comprises a first stage ofscanning the image and labeling with provisional identificationinformation, the first stage including the step of inputting and thestep of labeling, wherein the step of inputting of the first stageincludes inputting, together with the pixel block, an adjacent pixelgroup including pixels that are adjacent to the pixel block and havealready been labeled with the provisional identification information,and the step of labeling of the first stage includes the steps of:inheriting, when the adjacent pixel group includes inheritableprovisional identification information, the inheritable provisionalidentification information as the common identification information;recording, when the adjacent pixel group includes other inheritableprovisional identification information, connecting information for theinherited provisional identification information and non-inheritedprovisional identification information; and setting, when the adjacentpixel group does not include inheritable provisional identificationinformation, new provisional identification information as the commonidentification information.
 2. The method according to claim 1, whereinthe pixel block is composed of four pixels adjacent to one another intwo dimensions or eight pixels adjacent to one another in threedimensions.
 3. The method according to claim 1, further comprising: asecond stage of labeling with real identification information showingimage elements, after the first stage, wherein the second stage includesthe step of inputting and the step of labeling that are independent ofthe steps of inputting and labeling of the first stage respectively, andthe step of labeling of the second stage includes setting the realidentification information that is common to pixel blocks in aconnecting relationship by the connecting information, as the commonidentification information.
 4. The method according to claim 1, whereinin the step of inputting of the first stage, the pixel block composed offour pixels that are adjacent to one another in two dimensions and theadjacent pixel group composed of six pixels that are adjacent to twoadjacent edges of the pixel block are inputted, and in the step oflabeling of the first stage, when both the pixel block and the adjacentpixel group include pixels that constitute an image element in whichpixels are consecutive, the provisional identification informationincluded in the adjacent pixel group is inheritable.
 5. The methodaccording to claim 1, wherein in the step of inputting of the firststage, at least one pixel block and the adjacent pixel group includingpixel blocks that are adjacent to the at least one pixel block areinputted, and in the step of labeling of the first stage, when both theat least one pixel block and the adjacent pixel group include pixelsthat are the subjects for grouping, the provisional identificationinformation included in the adjacent pixel group is inheritable.
 6. Themethod according to claim 1, wherein in the step of inputting of thefirst stage, a large pixel block composed of four pixel blocks that areadjacent to one another in two dimensions and the adjacent pixel groupcomposed of six pixel groups that are adjacent to two adjacent edges ofthe large pixel block are inputted, and in the step of labeling of thefirst stage, when both the large pixel block and the adjacent pixelgroup include pixels that are the subjects for grouping, the provisionalidentification information included in the adjacent pixel group isinheritable.
 7. The method according to claim 6, further comprising asecond stage for labeling image elements with real identificationinformation, after the first stage, the second stage including the stepof inputting and the step of labeling that are independent of the stepof inputting and labeling of the first stage respectively, and whereinthe step of labeling of the second stage includes setting the realidentification information that is common to large pixel blocks in aconnecting relationship by the connecting information, as the commonidentification information and labeling all of the pixels that are thesubjects for grouping and are included in the large pixel block.
 8. Themethod according to claim 1, further including the step of calculatingcharacteristic values of respective image elements having a sameprovisional identification by repeatedly carrying out an operation inunits that include at least one pixel block.
 9. A system for generatinga labeled image, the system including: an interface configured forinputting data including a plurality of pixels, which are adjacent inmore than one dimension and constitute a pixel block, in parallel fromdata including pixels for forming an image; and a labeling processorconfigured for labeling, based on binarized pixels, all on-pixels or alloff-pixels that are subject for grouping and are included in the pixelblock with common identification information in parallel, wherein thesystem further comprises a first processing system for scanning an imageand labeling with provisional identification information, wherein thefirst processing system includes the interface, the labeling processorand a memory, the memory stores pixels that have already been labeledwith the provisional identification information, the interface of thefirst processing system is configured to input the pixel block and anadjacent pixel group including pixels that are adjacent to the pixelblock and stored in the memory as the pixels that have already beenlabeled with the provisional identification information, and thelabeling processor of the first processing system is configured forperforming: inheriting, when the adjacent pixel group includesinheritable provisional identification information, the inheritableprovisional identification information as the common identificationinformation; recording, when the adjacent pixel group includes otherinheritable provisional identification information, connectinginformation for the inherited provisional identification information andnon-inherited provisional identification information; setting, when theadjacent pixel group does not include inheritable provisionalidentification information, new provisional identification informationas the common identification information, and labeling, based onbinarized pixels, all on-pixels or all off-pixels that are subjects forgrouping and are included in the pixel block with common identificationinformation.
 10. The system according to claim 9, wherein the pixelblock is composed of four pixels adjacent to one another in twodimensions or eight pixels adjacent to one another in three dimensions.11. The system according to claim 9, comprising: a processor including aprocessing region that includes a plurality of processing elements, aplurality of data paths that operate in parallel being configured by theplurality of processing elements in the processing region, wherein theinterface and the labeling processor are configured in the processingregion.
 12. The system according to claim 9, wherein the labelingprocessor of the first processing system is configured for pipelineprocessing: a process that decodes the pixel block and the adjacentpixel group, and a process that labels the pixels for grouping in thepixel block with selected one of the inheritable provisionalidentification information and the new provisional identificationinformation as the common identification information.
 13. The systemaccording to claim 9, further comprising a second processing system forlabeling with real identification information showing image elements,the second processing system including the interface and the labelingprocessor that are configured independently of the first processingsystem, wherein the labeling processor of the second processing systemis configured to set the real identification information that is commonto the pixel blocks in a connecting relationship as the commonidentification information, based on the connecting information.
 14. Thesystem according to claim 9, wherein the interface of the firstprocessing system is configured to supply the pixel block composed offour pixels adjacent to one another in two dimensions and the adjacentpixel group composed of six pixels that are adjacent to two adjacentedges of the pixel block to the labeling processor of the firstprocessing system, and the labeling processor of the first processingsystem is configured to inhere, when both the pixel block and theadjacent pixel group include pixels that constitute an image element inwhich pixels are consecutive, the provisional identification informationincluded in the adjacent pixel group.
 15. The system according to claim9, wherein the interface of the first processing system is configured tosupply a large pixel block composed of four pixel blocks adjacent to oneanother in two dimensions and the adjacent pixel group composed of sixpixel blocks that are adjacent to two adjacent edges of the large pixelblock to the labeling processor of the first processing system, and thelabeling processor of the first processing system is configured toinhere, when both the large pixel block and the adjacent pixel groupinclude pixels for grouping, the provisional identification informationincluded in the adjacent pixel group.
 16. The system according to claim15, further comprising: a reconfigurable processor including aprocessing region that includes a plurality of processing elements, aplurality of data paths that operate in parallel being configured by theplurality of the processing elements in the processing region, and acontrol unit for reconfiguring the processing region, wherein theinterface and the labeling processor included in the first processingsystem and the interface and the labeling processor included in thesecond processing system are configured at different timing in theprocessing region.
 17. The system according to claim 15, furthercomprising a second processing system for labeling with realidentification information showing image elements, the second processingsystem including the interface and the labeling processor that areconfigured independently of the first processing system, wherein thelabeling processor of the second processing system is configured to set,based on the connecting information, the real identification informationthat is common to large pixel blocks in a connecting relationship as thecommon identification information and to label all of the pixels forgrouping included in the large pixel block.
 18. The system according toclaim 9, further comprising a processor configured to repeatedlyperforming an operations in units of at least one pixel block tocalculate a characteristic value of each image element that has a sameprovisional identification.